1.Read the design specification and keep it at hand.
2.Open the Codec manual?file?
sampling rate configuration, Tables 17-18;
configuration registers, Table 30; find what the values in codec_init template file mean;
software control interface (I2C or 2-wire MPU), Figures 8 and 34; the 2-wire mode and 0011010 device address modes are hardwired;
digital audio signal protocol, Figure 30, note timing in micro seconds.
3.For both digital audio and I2C interfaces draw the waveforms, add there the waveforms of any additional counters that form the necessary delays out of 50MHz clock, then draw the vertical lines for each output event and indicate conditions that trigger it. See my handout as an example.
4.Once you've formed the condition-action pairs, implement them within the provided code templates.
5.Read about synchronous parallel interfaces, look at my example of parallel protocol(file)
6.Simulate your design, try it on DE1 board.
7.Implement the FIR filter, simulate and try it on the board.
8.Measure the frequency response of the filter by using the standard lab equipment.
ATTENTION!!! Check if the license is set up in Quartus, modify this field if necessary:
Tools -> Options -> License Setup: ;
Attachments
FIR filter response.pdf
FIR coefficients.txt
WM8731 Codec data sheet.pdf
DE1 board user manual.pdf
old Cyclone II FPGA data sheet.pdf
template_codec_init.vhd
template_s2p_adaptor.vhd
old DE1 (Cyclone II) pin assignments.csv
Parallel interface specification.pdf
DE1_SoC (Cyclone V) board default pin assignments for audio applications (FPGA only).qsf
DE1_SoC (Cyclone V) board default pin assignments for SoC applications (processor+FPGA), audio included.qsf
new Cyclone V FPGA data sheet.pdf
?The file is in the compressed file of PartB?
Simulation Guide
A guide to simulating with Modelsim-Altera using the shift register example from the lecture. A test bench file is included.
Useful templates for test benches
Clock generator, 50MHz, only for the testbench:
clk_proc : PROCESS
variable i : integer;
BEGIN -- code that executes only once
for i in 1 to num_cycles loop -- specify here the length of the simulation run
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end loop;
WAIT;
END PROCESS;
Input test signal. You can have as many of these as needed, just use unique labels (e.g. stim_proc)
stim_proc : PROCESS
BEGIN
d <= '0';
wait for 45 ns;
d <= '1';
-- carry on adding wait-assignment pairs to capture the waveform
WAIT; -- do not repeat once finished
END PROCESS;
Attachments
modelsim_guide.doc
sr_vhd_tst.vht