Sequential circuit implementing serial addition

Consider the sequential circuit implementing serial addition built with two shift registers, a 1-bit full adder and a D flip-flop (Figure 6.5 in Morris Mano & Michael Ciletti, Digital Design). Design and implement in Verilog a 4-bit version of this circuit. Use the behavioral implementation behavioralserialadder.vl (attached) and make the following changes/additions:

1. Create a logic diagram of the circuit. Use Figure 6.5 and update it using the structure of the behavioral model (add a 2x1 multiplexer and parallel inputs to the shift registers).
2. Create a logic diagram of the shift register with parallel load as implemented in module shiftreg (block level multiplexers and D-flip-flops).
3. Implement modules shiftreg and serialadder at gate-level using gate-level D-flip-flops and 2x1 multiplexers (http://www.cs.ccsu.edu/~markov/ccsucourses/354Syllabus.html#Synchronous).
4. Test the circuit with several inputs (adding positive and negative numbers) and show the output.
5. Write a report, including the logic diagrams, the Verilog source code and the test results. The report must include your name.