Digital logic

Digital logic COIS 2320 Assignment 3.  This is worth 15% of your final Grade 1) Design a system with 2 4-bit shift registers with a bus (single wire) connecting the two. a)    Design the system so that the endianness (bit order) is retained b)    Design where the endianness is reversed 2) Design a system which has an array of memory in registers, with 4 rows of words, with a word length of 16 bits.   You can assume the existence of an 8-bit register as a primitive component you just draw as a box. a)    Design a system that will transfer data from any selected row into a shift register of the word size, preserving endianness. b)    Design a system that will transfer data from any selected row into a shift register of the word size that reverses byte ordering but not endianness c)    Design a system that will transfer data from any selected row that will transfer data into a shift register that reverses both byte order and endianness