CMOS Integrated Circuits
Design Assignment 2019
Dr Naser Sedghi
Department of Electrical Engineering and Electronics
Semester 2, 2019
[email protected]
CMOS Integrated Circuits. Design Assignment ELEC212 2
Design Assignment
• You are required to design a simple CMOS circuit consisting of a twoinput NOR or NAND gate, as part of this module.
• The details will be announced in vital at the end of next week.
• You will have three weeks (this year a bit more than 4 weeks) to
complete the design and hand it in as a hard copy on maximum four A4
pages.
• It has 25% of total marks (75% for final exam).
• The assignment includes:
• Calculations: Aspect ratio and actual channel length and width for
all transistors based on minimum feature size given. Feature sizes
and their separation.
• Explanation: Full explanation of your calculations and the choice of
actual dimensions.
• Layout: Drawing of the layout, including all layers and VDD and
ground lines.
CMOS Integrated Circuits. Design Assignment ELEC212 3
Layout (50%)
• The layout should be drawn using a graphical design or drawing software and
be printed in color on one sheet of A4 paper.
• Use only basic layers: n-well, active area, poly, n-select (ndiff), optional pdiff,
contact, metal.
• Use different colors and patterns for different layers.
• Use legends to clearly identify different layers.
• Make sure the layers underneath can be seen clearly.
• The layout should be on right scale, either in µm or ?.
• Turn the fine grids on and show the critical dimensions on the drawing.
• Manual drawing (not recommended) is acceptable only if it is of very high
quality, in color, and with correct scale.
• The layout design rules should be followed.
• Use the minimum possible area.
Do not sacrifice the design to minimize the area.
CMOS Integrated Circuits. Design Assignment ELEC212 4
Layout (50%)
Marks:
• Basic: 35%
• Penalties:
• Catastrophic misalignment: – 10%.
• Noncatastrophic misalignment: – 5%.
• Not in scale, no legends (or other ways to identify layers): – 5%.
• Optimum use of space: 5%.
• Applying layout design rules: 5%.
• Quality of drawing (using proper software, choice of colors and patterns, fine
grids, originality): 5%.
CMOS Integrated Circuits. Design Assignment ELEC212 5
Calculations (50%)
• Calculating the aspect ratio of all transistors using circuit design rules.
• Calculating the channel length and width of all transistors.
• Choosing the actual sizes in design.
• Calculating all feature sizes and their separation using layout design rules.
CMOS Integrated Circuits. Design Assignment ELEC212 6
Calculations (50%)
Marks:
• Correctness of calculations: 40%
• Aspect ratios, channel lengths and widths, choice of actual sizes: 25%.
• Feature sizes and applying layout design rules: 15%.
• Format, clarity, neatness, proper use of equations, units, etc.: 10%.
Examples:
??
?? ??
= 2.5
??
?? ??
(W/L)p = 2.5(W/L)n
(W/L)p = 2.5(W/L)n
(W/L)p=2.5(W/L)n
???? = 1.2 µm Lp = 2.5 µm Lp = 2.5 µm Lp=2.5 um
???? = 2.5 × 1.2 = 3 µm Wp = 2.5×1.2 = 3 µm Wp = 2.5*1.2 = 3
CMOS Integrated Circuits. Design Assignment ELEC212 7
Explanation
• All calculations, assumptions, and choices should be clearly explained.
• It is better calculations come in line with explanation text:
The aspect ratio of the PMOS is 2.5 times of that of NMOS, therefore:
(W/L)p = 2.5×2 = 5.
• The calculations related to layout and the design rules used should be
explained.
• Refer to the layout design if necessary.
• The explanations do not have separate marks; they are considered as part of
calculations. Higher marks go to correct calculations and good explanation.
• Better does not need more. All your work should not be more than 4 pages of
A4 paper.